An increase in the number of fabrication processes available for manufacturing integrated circuits has lead to an increased diversity in operating conditions under which the integrated circuits perform. For example, the range of supply voltages, switching voltages, input and output voltages can vary as between integrated circuits fabricated by different processes. In order for an integrated circuit to be compatible with circuits manufactured using a different process, it may therefore be necessary for the integrated circuit to be tolerant of voltages on the I/O connections thereof which are different from voltages which may be received from a circuit manufactured using the same fabrication process.
One particular problem which has been encountered is the application of a voltage to an I/O connection which is higher that the supply voltage for the integrated circuit. This is referred to as an overvoltage condition at the I/O connection. For example, complimentary metal oxide semiconductor (CMOS) circuits can be manufactured to operate on a supply voltage of 3 volts (where the rail to rail voltage swing is 3 volts), while many other circuits utilize a 5 volt supply and can thus be expected to produce an output in the region of 5 volts. If a 3 volt CMOS circuit receives an input of 5 volts at an I/O connection thereof (an overvoltage condition), difficulties can be encountered within an output buffer circuit of the 3 volt CMOS circuit. In particular, an undesirably large leakage current from the I/O connection through the output buffer of the 3 volt CMOS circuit may arise as a result of the overvoltage condition. Additionally, latch up of the CMOS circuit can occur as a result of the overvoltage condition. Both of these phenomena are detrimental to the operation of the CMOS circuit, and can in extreme circumstances result in destruction of the circuit.
A simplified CMOS output buffer circuit 2 is illustrated in FIG. 1 for driving an I/O connection 8, such as a contact pad of an integrated circuit (IC), which contains the buffer 2, in accordance with signals received on control lines 15. The circuit 2 comprises a PMOS pull up transistor 4 which couples the I/O connection 8 by way of an output line 11 (labeled OUT) to a supply voltage line 10 (labeled V.sub.CC). An NMOS pull down transistor 6 couples the I/O connection 8 to another supply voltage such as V.sub.SS or ground (GND). In operation, the pull up and pull down transistors 4, 6 are controlled by way of the control lines 15 so as to selectively couple the I/O connection 8 to the supply rail 10 or V.sub.SS /GND which enables the output voltage to swing between V.sub.SS (e.g. zero volts) and V.sub.CC (the supply voltage). In order for the output buffer circuit 2 to drive the I/O connection 8 all the way to the positive supply voltage V.sub.CC the pull up transistor 4 must be a PMOS type transistor in order to avoid the undesirable voltage drop which would occur were an NMOS type transistor is used for this function.
In a CMOS fabrication process, the PMOS and NMOS transistors which make up the integrated circuit are fabricated in separate regions of the silicon substrate, the P type transistors in an N type region, and the N type transistors in a P type region. One way in which this is achieved is to dope the semiconductor wafer with a P type majority carrier in which the N type transistors can be formed, and to form discrete N type "well" regions in which the P type transistors are fabricated, which is referred to as an n-well CMOS process. Typically the n-well substrate regions are biased to the supply voltage of the integrated circuit, which promotes proper operation of the transistors formed therein.
An equivalent circuit 20 of the output buffer circuit 2 is shown in FIG. 2, which illustrates a result of the application of an overvoltage condition to the I/O connection 8. An electrical apparatus 12 is shown connected to the buffer 2 by way of the I/O connection 8. The apparatus 12 may, for example, be another integrated circuit which operates at a higher supply voltage (e.g. 5 v) than the IC which contains buffer 2. When the electrical apparatus 12 raises the potential of output line 11 above the supply voltage V.sub.CC of the output buffer, the drain terminal of the pull up transistor 4 is raised above the potential of both the gate terminal thereof and the substrate region in which the transistor is formed. This causes the P type pull-up transistor 4 to turn on which creates a current path from the output line 11 to the supply line 10, and also causes the drain-substrate diode of the transistor 4 to be forward biased, creating another current path from the output line to the V.sub.CC supply line. These current paths are indicated by dashed lines in FIG. 2. This situation at best stops the voltage at the I/O connection from rising much above the V.sub.CC supply voltage of the IC which contains buffer 2, but can also cause CMOS latch-up in this integrated circuit because of the injected current.
A similar situation occurs during "hot" or "live insertion". In this case, the I/O connections of an integrated circuit device are assumed to be conditioned (i.e., non-zero voltage) before the power supply is connected thereto. Even though the voltage applied to the I/O connections may not be an overvoltage in the sense of being greater than the operating supply voltage of the device, the instantaneous voltage at the I/O connections is nevertheless greater than the voltage applied to the power supply line when power is connected (ramped) to the device. In this instance, a major concern is latch-up if excessive current is injected from the I/O connection.
It is apparent from the forgoing discussion that it is desirable to provide an output buffer circuit which is capable of tolerating the application of an overvoltage condition to the corresponding I/O connection, and which is capable of supporting "live-insertion" whilst minimizing the extent of current injection from the I/O connection when the electrical potential therein is greater than the potential at the power supply line of the buffer circuit. It is also desirable to provide such a buffer circuit using simple, N-well CMOS technology without necessarily requiring the use of bipolar technology and/or charge pumping circuits.